1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which can be advantageously applied for multi-port random access memories (RAMs).
2. Description of the Related Art
In recent years, with the digitalization of various kinds of electronic equipments, semiconductor memory devices have been used as indispensable components among various kinds of technical fields. Accordingly, a high reliability, a large capacity and a high speed process are required for such semiconductor memory devices, and the researches and developments in this field have been prosperously made. For example, U.S. Pat. No. 4,667,330 discloses such a semiconductor memory device as a related art.
FIG. 2 is a block diagram illustrating an arrangement of a conventional semiconductor memory device.
This semiconductor memory device incorporates a memory array 10 having a plurality of pairs of word lines 11-1, 11-2 . . . 11-m, 12-1, 12-2 . . . 12-m and a plurality of bit lines 13-1, 13-2 . . . 13-n, 14-1, 14-2 . . . 14-n. Memory cells 15-11 . . . 15-1n, 15-21 . . . 15-2n, 15-m1 to 15-mn for storing therein predetermined data, N-channel MOS type transistors 16-11, 16-1n, 16-21 to 16-2n, 16-m1 to 16-mn for writing data, and N-MOS 17-11 to 17-1n, 17-21 to 17-2n, 17-m1 to 17-mn are provided at cross points between these word lines and these bit lines, respectively.
Further, a read address generating circuit 18 is connected to the word lines 11-1 to 11-m to generate a read row address signal. A write address generating circuit 19 is connected to the word lines 12-1 to 12-m to generate a write address signal. A write data circuit 20 is connected to the bit lines 13-1 to 13-n to deliver data to be written.
A shift circuit 21 is connected to the bit lines 14-1 to 14-n. This circuit 21 shifts data delivered from the memory array 10 in accordance with a predetermined shift value 22a to obtain shifted output data S1, S2 to Sn. A shift value control circuit 22 is connected to the shift circuit 21 to deliver the predetermined shift value 22a. A register 23 is connected to the shift circuit 21. This register 23 also receives only an effective one among shift output data S1, S2 to Sn in accordance with an input enabling signal 24a. Further, the register 23 is connected thereto with an input control circuit 24 to deliver the above-mentioned input enabling signal 25.
Next, explanation will be made of operation in case data stored in, for example, memory cells 15-12, 15-22 to 15-m2 arranged in a column-wise direction are read onto the register 23. It is assumed that the memory cells 15-12, 15-22 to 15-m2 store therein data D12, D22 to Dm2, respectively.
When the read address generating circuit 18 enables only an address signal on the word line 11-1, the N-MOS transistors 17-11, 17-12 to 17-1n are turned on. As a result, data stored in the memory cells 15-11, 15-12 to 15-n are delivered to the bit lines 14-1, 14-2 to 14-n, respectively, and are received by the shift circuit 21. The shift circuit 21 shifts the above-mentioned data leftward by one bit in accordance with a shift value 22a delivered from the shift value control circuit 22, and then delivers the shift output data S1, S2 to Sn toward the register 23. However, only the shift output data S1 is input to the register 23 in accordance with an input enabling signal 24a delivered from the input control circuit 24. At this time, the shift output data S1 received by the register 23 is the data D12 in the memory cell 15-12.
Then, only a row address signal on the word line 11-2 is enabled to deliver data stored in the memory cells 15-21, 15-22 to 15-2n onto the bit lines 14-1, 14-n. The shift circuit 21 shifts the data by 0 bit in accordance with a shift value 22a delivered from the shift value control circuit 22, and delivers the shift output data S1, S2 to Sn to the register 23. Only the shift data S2 is received by the register 23 in accordance with an input enabling signal 24a delivered from the input control circuit 24. At this time, the shift output data S2 received by the register 23 is the data D22 in the memory cell 15-22. Accordingly, data D12, D22 are held on the register 23.
Thereafter, the similar operation is repeated until the data Dm2 in the memory cell 15-m2 is received by the register 23.
However, there has been such a problem that such a conventional semiconductor memory device requires the shift circuit 23, the shift value control circuit 22 and the register 23 and the input control circuit 24 to read data stored in memory cells in a column-wise direction. Accordingly, it is difficult to decrease the circuit scale.
Further, there has been another problem in that when data stored in the m memory cells arranged in a column direction are read out, the shift circuit 21, the shift value control circuit 22, the register 23 and the input control circuit 24 have to be operated by m cycles, and accordingly, the process speed becomes slow.